1. Field of the Invention
The present invention relates to semiconductor memory devices, and in particular, to non-volatile semiconductor Electrically Erasable Programmable Read-Only Memory (EEPROM) cells.
2. Description of the Related Art
There are different kinds of EEPROM device for various types of application. For the case where high density integration of memory cells is essential, there is one type of EEPROM circuit that connects the individual memory cells in a NAND structure. Data are written in and read out of the memory cells serially. FIG. 1a is a top plan view of such a circuit. FIG. 1b is a cross-sectional side view taken along line 1b--1b of FIG. 1a. As is shown, each memory cell relies on thick field oxide regions 12 for cell-to-cell isolations. Disposed atop thin tunneling oxide 13 and portions of field oxide 12 is a polysilicon floating gate 14. Overlying floating gate 14 is a control gate 16. An insulating layer 15 is disposed in between floating gate 14 and control gate 16. Drain 17, source 18, and channel 11, which together constitutes a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) 9, are also formed in the semiconductor substrate 10. FIG. c is a schematic representation of the memory cell shown in FIGS. 1a and 1b, in which the alphabets G, D, and S are used to represent control gate 16, drain 17 and source 18, respectively. FIG. 2 shows the memory cells of FIGS. 1a and 1b arranged in a NAND structure, in which a plurality of memory cells are connected in series. As is shown, sources S and drains D of the adjacent cells in a column are connected together to form bitlines BL0 and BL1. In a similar manner, gates G of the memory cells in a row are connected together to form control lines CG1, CG2, . . . , and CG8. There are also control transistors without any floating gates primarily implemented for the addressing of the memory cells. These control transistors are controlled by select lines such as SG1 and SG2. Examples of this type of EEPROM circuit can be found in Shirota et al., entitled "A 2.3 um.sup.2 Memory Cell Structure for 16Mb NAND EEPROMs", IEDM 1990, Technical Digest, pp 103-106; and in Momodomi et al., entitled "New Device Technologies For 5V-Only 4Mb EEPROM With NAND Structure CEll" IEDM 1988, Technical Digest, pp 412- 415.
As with most EEPROM circuits, circuits of the aforementioned type utilize the Fowler-Nordheim Tunneling (FNT) effect for the programming (or writing) and deprogramming (or erasure) of the memory cells.
Deprogramming is a process of setting the threshold voltage of the MOSFET in each of the memory cells to a predetermined value, depending on the logic convention used in the EEPROM circuit. For example, in this case, either a +2 Volts or a -2 Volts threshold voltage of the MOSFET can be used to correspond the logical bit "0". To deprogram the memory cells such that each of the MOSFETs 9 assumes a threshold voltage of +2 Volts, all control lines CG1-CG8 are energized to +22 Volts and the substrate is tied to the ground potential. Through the process of capacitive coupling, each of the floating gates 14 is coupled with a +11 Volts potential, for example. The +11 Volts voltage at floating gate 14 is sufficient to attract electrons from channel 11 through thin tunneling oxide layer 13 via the FNT effect. As a result, the channel 14 is depleted of electrons and MOSFET 9 assumes a threshold voltage of +2 Volts. To deprogram the memory cells such that each of the MOSFET's threshold voltage falls below the ground potential to -2 Volts. The mechanism is similar as mentioned above except that the source 18 now needs to be electrically connected to a potential of approximately +20 Volts and the control lines CG1-CG8 are tied to the ground potential.
Programming is the reverse of deprogramming. Again, depending on the logic convention used in the EEPROM circuit, if a +2 Volts threshold for the MOSFET 9 in each of the memory cells is used to correspond a logical bit "0", for example, programming is the process of reversing the threshold voltage to -2 Volts. Alternatively, if the -2 Volts threshold for the MOSFET 9 in each of the memory cells is used to correspond a logical bit "0", programming is the process of reversing the threshold voltage to +2 Volts. For the sake of a concise and clear illustration, only the latter case is herein elaborated. That is, to reverse the deprogrammed threshold voltage of -2 Volts to +2 Volts, a +18 Volts is first applied to the control lines CG1-CG8 of the selected memory cell. Through the process of capacitive coupling, each floating gate is coupled with +10 Volts. At the same time, control lines CG1--CG8 of unselected memory cells are tied to +7 Volts. Again, through the process of capacitive coupling, each floating gate is approximately coupled with +4 Volts, which is insufficient to cause any FNT effect. Select lines SG1 and SG2, are then powered up to +7 Volts and 0 Volt, respectively. Moveover, bitlines BL0 and BL1 are electrically connected to +7 Volts while source line SL is tied to the ground potential. Selected memory cells with a coupled +10 Volts at the floating gate 14 is sufficient to attract electrons from the underlying channel via the FNT effect. The channel is then depleted of electrons and as a consequence, the MOSFET 9 in each of the selected memory cells changes to -2 Volts. It should be note that memory cells in a column are connected in a NAND structure, as shown in FIG. 2. For this reason, each of the memory cells needs to be programmed sequentially such that each memory cell is first programmed to be conductive and acts as a conducting path between the source line and the subsequent cells. In this case, the first cell to be programmed is the cell connected to control line CG1 and the last cell to be programmed is the cell connected to control line CG8.
As is shown, the high integration feature of the memory cells is compromised by the complexity of the programming process. Each memory cell in the array can not be randomly and individually accessed. This restriction causes much inconvenience during applications.
It is accordingly an objective of the present invention to provide a non-volatile semiconductor memory circuit in which each memory cell can be programmed or deprogrammed randomly without resorting to identify a block of cells and the addressing each of the cells sequentially. Another objective is to provide a memory cell with a high gate capacitance coupling ratio which further speeds up the programming and deprogramming processes.
These and other objectives are accomplished by an unique structural design of the memory cell of the present invention.